1. Field of the Invention
The disclosed embodiments relate to memory systems and, more particularly, to a memory system incorporating a circuit for generating a delay signal to be used in read operation timing (e.g., wordline pulse timing and/or sense amplifier set signal timing) and an associated method of operating such a memory system.
2. Description of the Related Art
As mentioned above, memory systems generally comprise an array of essentially identical memory cells (e.g., static random access memory (SRAM) cells, ternary content-addressable memory (TCAM) cells, dynamic random access memory (DRAM) cells, non-volatile random access memory (NVRAM) cells, etc.) that store data values. Depending upon the type of memory cell, different steps may be performed during read operations to determine the stored data values. However, regardless of the type of memory cell, a read operation typically involves the activation of a wordline and, thereby the turning on of at least one access transistor (also referred to herein as a pass gate transistor) for a memory cell followed by the subsequent sensing by a sense amplifier of a charge on at least one bitline connected to the memory cell. For read operation accuracy (i.e., read operation stability), the timing of both the wordline pulse that activates the wordline and the sense amplifier set signal that activates the sense amplifier are critical to ensure that there is a sufficient amount of time delay between when the wordline is activated and when the sense amplifier senses the charge on the bitline(s) to ensure that the stored data value is properly read.
Wordline pulse timing and sense amplifier set signal timing are typically provided by a delay signal output by a delay signal generator. Historically, such delay signal generators incorporate logic devices to output a delay signal with some preset amount of time delay and this preset amount of delay is calculated based on the design of the memory cell. However, manufacturing process variations, temperature variations and/or voltage variations can result in a memory array with memory cells having a relatively large range of required time delays between wordline activating and sense amplifier sensing, particularly as memory cell sizes continue to be scaled. Therefore, recently, delay signal generators have been developed that generate a delay signal having a time delay which tracks the average time delay required by the memory cells. While such tracking delay signal generators provide for greater read operation stability over fixed delay signal generators that simply provide a delay signal with a preset amount of delay, they do not guarantee the read functionality of statistically slow memory cells.